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| SN54HC4060, SN74HC4060 14 STAGE ASYNCHRONOUS BINARY COUNTERS AND OSCILLATORS SCLS161D - DECEMBER 1982 - REVISED SEPTEMBER 2003 D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-A Max ICC Typical tpd = 14 ns SN54HC4060 . . . J OR W PACKAGE SN74HC4060 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) D 4-mA Output Drive at 5 V D Low Input Current of 1 A Max D Allow Design of Either RC- or Crystal-Oscillator Circuits SN54HC4060 . . . FK PACKAGE (TOP VIEW) NC - No internal connection description/ordering information The 'HC4060 devices consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC- or crystal-oscillator circuits. A high-to-low transition on the clock (CLKI) input increments the counter. A high level at the clear (CLR) input disables the oscillator (CLKO goes high and CLKO goes low) and resets the counter to zero (all Q outputs low). ORDERING INFORMATION TA PDIP - N PACKAGE Tube of 25 Tube of 40 SOIC - D -40 C 85C -40C to 85 C SOP - NS SSOP - DB Reel of 2500 Reel of 250 Reel of 2000 Reel of 2000 Tube of 90 TSSOP - PW CDIP - J -55 C 125C -55C to 125 C CFP - W Reel of 2000 Reel of 250 Tube of 25 Tube of 150 ORDERABLE PART NUMBER SN74HC4060N SN74HC4060D SN74HC4060DR SN74HC4060DT SN74HC4060NSR SN74HC4060DBR SN74HC4060PW SN74HC4060PWR SN74HC4060PWT SNJ54HC4060J SNJ54HC4060W SNJ54HC4060J SNJ54HC4060W HC4060 HC4060 HC4060 HC4060 TOP-SIDE MARKING SN74HC4060N LCCC - FK Tube of 55 SNJ54HC4060FK SNJ54HC4060FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 QD GND NC CLKO CLKO QL QM QN QF QE QG QD GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC QJ QH QI CLR CLKI CLKO CLKO QN QF NC QE QG 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 NC VCC QJ QH QI NC CLR CLKI QM QL 1 SN54HC4060, SN74HC4060 14 STAGE ASYNCHRONOUS BINARY COUNTERS AND OSCILLATORS SCLS161D - DECEMBER 1982 - REVISED SEPTEMBER 2003 FUNCTION TABLE (each buffer) INPUTS CLK X CLR L L H FUNCTION No change Advance to next stage All outputs L logic diagram (positive logic) R T R T R T R T R T R T R T R T R T 4 QF 6 QG 14 QH 13 QI 15 QJ 1 QL 2 QM 3 QN CLR 12 R T 9 CLKO CLKO 7 QD 5 QE R T R T R T R T CLKI 11 10 Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54HC4060, SN74HC4060 14 STAGE ASYNCHRONOUS BINARY COUNTERS AND OSCILLATORS SCLS161D - DECEMBER 1982 - REVISED SEPTEMBER 2003 recommended operating conditions (see Note 3) SN54HC4060 MIN VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO t/v Low-level input voltage Input voltage Output voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 0 0 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 0 0 NOM 5 MAX 6 SN74HC4060 MIN 2 1.5 3.15 4.2 0.5 1.35 1.8 VCC VCC 1000 500 400 ns V V V V NOM 5 MAX 6 UNIT V High-level input voltage Input transition rise/fall time TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 2V All outputs VOH Q outputs VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 A IOL = 4 mA IOL = 5.2 mA IO = 0 VI = VIH or VIL, IOH = -20 A 4.5 V 6V 4.5 V 6V 2V All outputs VOL Q outputs II ICC Ci VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, VI = VIH or VIL, 4.5 V 6V 4.5 V 6V 6V 6V 2 V to 6 V 3 TA = 25C MIN TYP MAX 1.9 4.4 5.9 3.98 5.48 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 0.1 0.1 0.1 0.1 0.26 0.26 100 8 10 SN54HC4060 MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1000 160 10 MAX SN74HC4060 MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1000 80 10 nA A pF V V MAX UNIT POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54HC4060, SN74HC4060 14 STAGE ASYNCHRONOUS BINARY COUNTERS AND OSCILLATORS SCLS161D - DECEMBER 1982 - REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC 2V fclock Clock frequency 4.5 V 6V 2V CLKI high or low tw Pulse duration CLR high 4.5 V 6V 2V 4.5 V 6V 2V tsu Setup time, CLR inactive before CLKI 4.5 V 6V 90 18 15 90 18 15 160 32 27 TA = 25C MIN MAX 5.5 28 33 135 27 23 135 27 23 240 48 41 SN54HC4060 MIN MAX 3.7 19 22 115 23 20 115 23 20 200 40 34 ns ns SN74HC4060 MIN MAX 4.3 22 25 MHz UNIT switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V fmax 4.5 V 6V 2V tpd CLKI QD 4.5 V 6V 2V tPHL CLR Any Q 4.5 V 6V 2V tt Any 4.5 V 6V TA = 25C MIN TYP MAX 5.5 28 33 10 45 53 240 58 42 66 18 14 28 8 6 490 98 83 140 28 24 75 15 30 SN54HC4060 MIN 3.7 19 22 735 147 125 210 42 36 110 22 19 MAX SN74HC4060 MIN 4.3 22 25 615 123 105 175 35 30 95 19 16 ns ns ns MHz MAX UNIT operating characteristics, TA = 25C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP 88 UNIT pF 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54HC4060, SN74HC4060 14 STAGE ASYNCHRONOUS BINARY COUNTERS AND OSCILLATORS SCLS161D - DECEMBER 1982 - REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL = 50 pF (see Note A) LOAD CIRCUIT VCC 50% tPLH In-Phase Output 50% 10% tPHL Out-of-Phase Output 90% 50% 10% tf 90% tr tPLH 50% 10% 90% tr 50% 0V tPHL 90% VOH 50% 10% VOL tf VOH VOL Low-Level Pulse 50% Data Input 50% 10% Reference Input tsu 90% 90% VCC 50% 10% 0 V tf 50% VCC 0V tr Input VOLTAGE WAVEFORMS SETUP AND INPUT RISE AND FALL TIMES High-Level Pulse VCC 50% tw VCC 50% 0V VOLTAGE WAVEFORMS PULSE DURATIONS 50% 0V VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54HC4060, SN74HC4060 14 STAGE ASYNCHRONOUS BINARY COUNTERS AND OSCILLATORS SCLS161D - DECEMBER 1982 - REVISED SEPTEMBER 2003 CONNECTING AN RC-OSCILLATOR CIRCUIT TO THE 'HC4060 DEVICES The 'HC4060 devices consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC- or crystal-oscillator circuits. When an RC-oscillator circuit is implemented, two resistors and a capacitor are required. The components are attached to the terminals as shown: 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 R2 R1 C To determine the values of capacitance and resistance necessary to obtain a specific oscillator frequency (f), use this formula: f+ 1 2(R1)(C) 0.405 R2 R1)R2 ) 0.693 If R2 > > R1 (i.e., R2 = 10R1), the above formula simplifies to: f + 0.455 RC 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) 28 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER 18 17 16 15 14 13 12 NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20 A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6) B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0) 19 20 21 B SQ 22 A SQ 23 24 25 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 0.045 (1,14) 0.035 (0,89) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL MPDI002C - JANUARY 1995 - REVISED DECEMBER 20002 N (R-PDIP-T**) 16 PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE PINS ** DIM A 16 9 A MAX 14 0.775 (19,69) 0.745 (18,92) 16 0.775 (19,69) 0.745 (18,92) 18 0.920 (23,37) 0.850 (21,59) 20 1.060 (26,92) 0.940 (23,88) A MIN 0.260 (6,60) 0.240 (6,10) C MS-100 VARIATION AA BB AC AD 1 0.070 (1,78) 0.045 (1,14) D 8 0.045 (1,14) 0.030 (0,76) D 0.020 (0,51) MIN 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gauge Plane 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0.430 (10,92) MAX 14/18 PIN ONLY 20 pin vendor option D 4040049/E 12/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001 D (R-PDSO-G**) 8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25) PLASTIC SMALL-OUTLINE PACKAGE 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.008 (0,20) NOM Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40) 0.010 (0,25) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** DIM A MAX A MIN 8 0.197 (5,00) 0.189 (4,80) 14 0.344 (8,75) 0.337 (8,55) 16 0.394 (10,00) 0.386 (9,80) 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M PLASTIC SMALL-OUTLINE 0,25 0,09 5,60 5,00 8,20 7,40 Gage Plane 1 A 14 0- 8 0,25 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** DIM A MAX 14 16 20 24 28 30 38 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,65 14 8 0,30 0,19 0,10 M 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50 Seating Plane 1,20 MAX 0,15 0,05 0,10 PINS ** DIM A MAX 8 14 16 20 24 28 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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